1. Field of the Invention
The embodiments of the invention generally relate to intra-process monitoring circuits and, more particularly, to an integrated circuit (IC) chip design and manufacturing system and an associated design and manufacturing flow method that provide for chip design analysis and insertion of on-chip and/or within scribe line intra-process monitoring circuits.
2. Description of the Related Art
As lithographic geometries are reduced for each successive semiconductor process generation, the effects of process variability have become significant first order issues. Designers are faced with creating tradeoffs between timing margin, power, and performance. Tighter process controls would enable lower power, higher performance, and/or higher yielding products. The ability to control processes to tighter tolerances is limited by an inability to obtain actual inline (i.e., intra-process) integrated circuit parameter measurements for a given wafer or die or for a given site on a given wafer or die.
Current techniques for taking integrated circuit parameter measurements utilize wired mechanical probing systems. For example, a standard probe with multiple pads (e.g., 25 pads) is used to probe a given kerf having a multitude of corresponding pad sets (e.g., 25 pad sets), according the number of macros that are available for measurements. The number of sites sampled per wafer lot is typically minimized due to the time and expense associated with such mechanical probing, the available capacity at the probing stations, and the invariable mechanical damage imparted on probed sites. These kerf measurements are used for wafer disposition and for both feedforward and feedback control loops to adjust manufacturing variables for control of such parameters.
Unfortunately, the limited frequency and number of sites sampled limits the tightness of control through such historical methods. Additionally, in-situ measurement during actual wafer processing is prevented, thereby eliminating the possibility of live process adjustment and/or end point detection based on direct on wafer parametric measurement. To solve this problem, U.S. patent application Ser. No. 12/053,705 disclosed embodiments of a system that incorporates passive on-wafer (i.e., on-chip and/or within scribe line) circuits that allow for wireless and dynamic intra-process (i.e., during and/or between process steps) measurements of integrated circuit parameters. Given the disclosed intra-process monitoring circuits of U.S. patent application Ser. No. 12/053,705 as well as other similar intra-process monitoring circuits, there is also now a need in the art for an improved design and manufacturing system as well as an improved design and manufacturing flow method that provide for chip design analysis and on-chip or within scribe line insertion of intra-process monitoring circuitry.